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| 1 p/n:pm1085 rev. 1.0, mar. 18, 2004 mx28f160c3bt/b 16m-bit [1m x16] cmos single voltage 3v only flash memory - word write suspend to read - sector erase suspend to word write - sector erase suspend to read register report ? automatic sector erase, word write and sector lock/ unlock configuration status reply - detection of program and erase operation comple- tion. - command user interface (cui) - status register (sr) data protection performance - include boot sectors and parameter and main sectors to be locked/unlocked 100,000 minimum erase/program cycles common flash interface (cfi) 128-bit protection register - 64-bit unique device identifier - 64-bit user-programmable latch-up protected to 100ma from -1v to vcc+1v package type: - 48-pin tsop (12mm x 20mm) - 48-ball csp (8mm x 6mm) features bit organization: 1,048,576 x 16 single power supply operation - vcc=vccq=2.7~3.6v for read, erase and program operation - vpp=12v for fast production programming - operating temperature:-40 c~85 c fast access time : 70/90ns low power consumption - 9ma typical active read current, f=5mhz - 18ma typical program current (vpp=1.65~3.6v) - 21ma typical erase current (vpp=1.65~3.6v) - 7ua typical standby current under power saving mode sector architecture - sector structure : 4kword x 2 (boot sectors), 4kword x 6 (parameter sectors), 32kword x 31 (main sectors) - top/bottom boot auto erase and auto program - automatically program and verify data at specified address - auto sector erase at specified sector automatic suspend enhance general description the mx28f160c3bt/b is a 16-mega bit flash memory organized as 1m words of 16 bits. the 1m word of data is arranged in eight 4kword boot and parameter sectors, and thirty-one 32k word main sectors which are indi- vidually erasable. mxic's flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. the mx28f160c3bt/b is packaged in 48-pin tsop and 48-ball csp. it is designed to be re- programmed and erased in system or in standard eprom programmers. the standard mx28f160c3bt/b offers access time as fast as 70ns, allowing operation of high-speed micropro- cessors without wait states. mxic's flash memories augment eprom functionality with in-circuit electrical erasure and programming. the mx28f160c3bt/b uses a command register to man- age this functionality. the command register allows for 100% ttl level control inputs and fixed power supply levels during erase and programming, while maintaining maximum eprom compatibility. mxic flash technology reliably stores memory contents even after 100,000 erase and program cycles. the mxic cell is designed to optimize the erase and programming
2 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 mechanisms. in addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cy- cling. the mx28f160c3bt/b uses a 2.7v~3.6v vcc supply to perform the high reliability erase and auto program/erase algorithms. the highest degree of latch-up protection is achieved with mxic's proprietary non-epi process. latch-up pro- tection is proved for stresses up to 100 milliamps on address and data pin from -1v to vcc + 1v. the dedicated vpp pin gives complete data protection when vpp< vpplk. a command user interface (cui) serves as the inter- face between the system processor and internal opera- tion of the device. a valid command sequence written to the cui initiates device automation. an internal write state machine (wsm) automatically executes the algo- rithms and timings necessary for erase, word write and sector lock/unlock configuration operations. a sector erase operation erases one of the device's 32k- word sectors typically within 1.0s, 4k-word sectors typi- cally within 0.5s independent of other sectors. each sec- tor can be independently erased minimum 100,000 times. sector erase suspend mode allows system software to suspend sector erase to read or write data from any other sector. writing memory data is performed in word increments of the device's 32k-word sectors typically within 0.8s and 4k-word sectors typically within 0.1s. word program sus- pend mode enables the system to read data or execute code from any other memory array location. mx28f160c3bt/b features with individual sectors lock- ing by using a combination of bits thirty-nine sector lock- bits and wp#, to lock and unlock sectors. the status register indicates when the wsm's sector erase, word program or lock configuration operation is done. the access time is 70/90/110ns (telqv) over the oper- ating temperature range (-40 c to +85 c) and vcc sup- ply voltage range of 2.7v~3.6v. mx28f160c3bt/b's power saving mode feature sub- stantially reduces active current when the device is in static mode (addresses not switching). in this mode, the typical iccs current is 7ua (cmos) at 3.0v vcc. as ce# and reset# are at vcc, icc cmos standby mode is enabled. when reset# is at gnd, the reset mode is enabled which minimize power consumption and provide data write protection. a reset time (tphqv) is required from reset# switch- ing high until outputs are valid. similarly, the device has a wake time (tphel) from reset#-high until writes to the cui are recognized. with reset# at gnd, the wsm is reset and the status register is cleared. 3 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 block diagram output buffer output multiplexer data register dq0-dq15 identifier register command user interface input buffer status register data comparator y-gating 32k-word main sector x31 ....... ....... boot sector 0 boot sector 1 parameter sector 0 parameter sector 1 parameter sector 2 parameter sector 3 parameter sector 4 parameter sector 5 main sector 0 main sector 1 main sector 29 main sector 30 write state machine program/erase voltage switch y decoder input buffer a0~a19 address latch address counter x decoder i/o logic vcc ce# we# oe# reset# wp# vpp vcc gnd 4 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 pin configurations 48 tsop (standard type) (12mm x 20mm) 48 ball csp (8mm x 6mm) top view, ball down for mx28f160c3bt/bxa (ball pitch=0.75mm, ball width=0.35mm) a15 a14 a13 a12 a11 a10 a9 a8 nc nc we# reset# vpp wp# a19 a18 a17 a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a16 vccq gnd q15 q7 q14 q6 q13 q5 q12 q4 vcc q11 q3 q10 q2 q9 q1 q8 q0 oe# gnd ce# a0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 mx28f160c3bt/b a1 a13 a2 a11 a3 a8 a4 vpp a5 wp# a6 a19 b1 a14 b2 a10 b3 we# b4 reset# b5 a18 b6 a17 c1 a15 c2 a12 c3 a9 c4 nc c5 nc c6 a6 d1 a16 d2 dq14 d3 dq5 d4 dq11 d5 dq2 d6 dq8 e1 vccq e2 dq15 e3 dq6 e4 dq12 e5 dq3 e6 dq9 f1 gnd f2 dq7 f3 dq13 f4 dq4 f5 vcc f6 dq10 a7 a7 a8 a4 b7 a5 b8 a2 c7 a3 c8 a1 d7 ce# d8 a0 e7 dq0 e8 gnd f7 dq1 f8 oe# 8.0 mm 6.0 mm 5 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 table 1. pin description symbol type description and function a0-a19 input address inputs for memory address. data pin float to high-impedance when the chip is deselected or outputs are disable. addresses are internally latched during a write or erase cycle. dq0-dq15 input/output data inputs/outputs: inputs array data on the second ce# and we# cycle during a program command. data is internally latched. outputs array and configuration data. the data pin float to tri-state when the chip is de-selected. ce# input chip enable : activates the device's control logic, input buffers, and sense amplifiers. ce# high de-selects the memory device and reduce power consumption to standby level. ce# is active low. reset# input reset/deep power down: when reset#=vil, the device is in reset/deep power down mode, which drives the outputs to high z, resets the wsm and minimizes current level. when reset#=vih, the device is normal operation. when reset# transitions from vil to vih, the device defaults to the read array mode. we# input wr ite enable: to control write to cui and array sector. we#=vil becomes active. the data and addresses are latched on the rising edge of the second we# pulse. vpp input/supply program/erase power supply:(1.65v~3.6v or 11.4v~12.6v) lower vpp 7 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 sector structure (bottom) sector sector size address range (h) boot sector 0 4k word 00000 ~ 00fff boot sector 1 4k word 01000 ~ 01fff parameter sector 0 4k word 02000 ~ 02fff parameter sector 1 4k word 03000 ~ 03fff parameter sector 2 4k word 04000 ~ 04fff parameter sector 3 4k word 05000 ~ 05fff parameter sector 4 4k word 06000 ~ 06fff parameter sector 5 4k word 07000 ~ 07fff main sector 0 32k word 08000 ~ 0ffff main sector 1 32k word 10000 ~ 17fff main sector 2 32k word 18000 ~ 1ffff main sector 3 32k word 20000 ~ 27fff main sector 4 32k word 28000 ~ 2ffff main sector 5 32k word 30000 ~ 37fff main sector 6 32k word 38000 ~ 3ffff main sector 7 32k word 40000 ~ 47fff main sector 8 32k word 48000 ~ 4ffff main sector 9 32k word 50000 ~ 57fff main sector 10 32k word 58000 ~ 5ffff main sector 11 32k word 60000 ~ 67fff main sector 12 32k word 68000 ~ 6ffff main sector 13 32k word 70000 ~ 77fff main sector 14 32k word 78000 ~ 7ffff main sector 15 32k word 80000 ~ 87fff main sector 16 32k word 88000 ~ 8ffff main sector 17 32k word 90000 ~ 97fff main sector 18 32k word 98000 ~ 9ffff main sector 19 32k word a0000 ~ a7fff main sector 20 32k word a8000 ~ affff main sector 21 32k word b0000 ~ b7fff main sector 22 32k word b8000 ~ bffff main sector 23 32k word c0000 ~ c7fff main sector 24 32k word c8000 ~ cffff main sector 25 32k word d0000 ~ d7fff main sector 26 32k word d8000 ~ dffff main sector 27 32k word e0000 ~ e7fff main sector 28 32k word e8000 ~ effff main sector 29 32k word f0000 ~ f7fff main sector 30 32k word f8000 ~ fffff 8 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 2 principles of operation the product includes an on-chip wsm to manage sec- tor erase, word write and lock-bit configuration functions. after initial device power-up or return from reset mode (see section on bus operations), the device defaults to read array mode. manipulation of external memory con- trol pins allow array read, standby and output disable operations. status register and identifier codes can be accessed through the cui independent of the vpp voltage. all functions associated with altering memory contents - sector erase, word write, sector lock/unlock, status and identifier codes - are accessed via the cui and verified through the status register. commands are written using standard microprocessor write timings. the cui contents serve as input to the wsm, which controls the sector erase, word write and sector lock/unlock. the internal algorithms are regulated by the wsm, including pulse repetition, internal verifica- tion and margining of data. addresses and data are in- ternally latched during write cycles. address is latched at falling edge of ce# and data latched at rising edge of we#. writing the appropriate command outputs array data, accesses the identifier codes or outputs status register data. interface software that initiates and polls progress of sector erase, word write and sector lock/unlock can be stored in any sector. this code is copied to and executed from system ram during flash memory updates. after successful completion, reads are again possible via the read array command. sector erase suspend allows system software to suspend a sector erase to read/write data from/to sectors other than that which is suspend. word write suspend allows system software to suspend a word write to read data from any other flash memory array location. with the mechanism of sector lock, memory contents cannot be altered due to noise or unwanted operation. when reset#=vih and vcc 10 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 4 command definitions the flash memory has four read modes: read array, read configuration, read status, read query, and two write modes: program, erase. these read modes are acces- sible independent of the vpp voltage. but write modes are disable during vpp 12 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 4.1 read array command upon initial device power-up and after exit from reset mode, the device defaults to read array mode. this op- eration is also initiated by writing the read array com- mand. the device remains enabled for reads until an- other command is written. once the internal wsm has started a sector erase, word write or sector lock con- figuration the device will not recognize the read array command until the wsm completes its operation unless the wsm is suspended via a sector erase suspend or word write suspend command. if reset#=vil device is in read read array command mode, this read opera- tion no longer requires vpp. the read array command functions independently of the vpp voltage and reset# can be vih. 4.2 read configuration codes command the configuration code operation is initiated by writing the read configuration codes command (90h). to re- turn to read array mode, write the read array command (ffh). following the command write, read cycles from addresses shown in table 4 retrieve the manufacturer, device, sector lock configuration codes and the protec- tion register(see table 4 for configuration code values). to terminate the operation, write another valid command. like the read array command, the read configuration codes command functions independently of the vpp voltage and reset# can be vih. following the read configuration codes command, the information is shown: code address data (a19-a0) (dq15-dq0) manufacturer code 00000h 00c2h device code(top/bottom) 00001h 88c2/88c3h sector lock configuration xx002h lock - sector is unlocked dq0=0 - sector is locked dq0=1 - sector is locked-down dq1=1 protection register lock 80 pr-lk protection register 81-88 pr table 4: id code 4.3 read status register command cui writes read status command (70h). the status reg- ister may be read to determine when a sector erase, word write or lock-bit configuration is complete and whether the operation completed successfully. (refer to table 6) it may be read at any time by writing the read status register command. after writing this command, all subsequent read operations output data from the sta- tus register until another valid command is written. the status register contents are latched on the falling edge of ce# or oe#, whichever occurs last. ce# or oe# must toggle to vih before further reads to update the status register latch. the read status register command func- tions independently of the vpp voltage. reset# can be vih. 4.4 clear status register command status register bits sr.5, sr.4, sr.3 or sr.1 are set to "1"s by the wsm and can only be reset by the clear status register command (50h). these bits indicate various failure conditions (see table 6). by allowing sys- tem software to reset these bits, several operations (such as cumulatively erasing multiple sectors or writing sev- eral words in sequence) may be performed. the status register may be polled to determine if an error occurred during the sequence. to clear the status register, the clear status register command (50h) is written on cui. it functions indepen- dently of the applied vpp voltage. reset# can be vih. this command is not functional during sector erase or word write suspend modes. 13 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 4.5 sector erase command erase is executed one sector at a time and initiated by a two-cycle command. a sector erase setup is first writ- ten (20h), followed by a sector erase confirm (d0h). this command sequence requires appropriate sequencing and an address within the sector to be erased. sector pre- conditioning, erase, and verify are handled internally by the wsm. after the two-cycle sector erase sequence is written, the device automatically outputs status register data when read (see figure 8). the cpu can detect sec- tor erase completion by analyzing the output data of the status register bit sr.7. when the sector erase is complete, status register bit sr.5 should be checked. if a sector erase error is de- tected, the status register should be cleared before sys- tem software attempts corrective actions. the cui re- mains in read status register mode until a new com- mand is issued. this two-step command sequence of set-up followed by execution ensures that sector contents are not acciden- tally erased. an invalid sector erase command sequence will result in both status register bits sr.4 and sr.5 being set to "1". also, reliable sector erasure can only occur when 2.7v~3.6v and vpp=vpp1/2. in the absence of this high voltage, sector contents are protected against erasure. if sector erase is attempted while vpp 15 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 4.9 sector lock/unlock /lockdown command 4.9.1 sector locked state the default status of all sectors upon power-up or reset is locked. any attempt on program or erase operations will result in an error on bit sr.1 of a locked sector. the status of a locked sector can be changed to unlocked or lock-down using software commands. an unlocked sec- tor can be locked by writing the sector lock command sequence, 60h followed by 01h. 4.9.2 sector unlocked state an unlocked sector can be programmed or erased. all unlocked sector return to the locked state when the de- vice is either reset or powered down. the status of an unlocked sector can be changed to locked or locked- down using software commands. a locked sector can be unlocked by writing unlock command sequence, 60h followed by d0h. 4.9.3 sector locked-down state sectors which are locked-down are protected from pro- gram and erase operation; however, the protection sta- tus of these sectors cannot be changed using software commands alone. any sector locked or unlocked can be locked-down by writing the lock-down command se- quence, 60h followed by 2fh. when the device is reset or powered down, the locked-down sectors will revert to the locked state. the status of wp# will determine the function of sector lock-down and is summarized is followed: wp# sector lock-down description wp#=0 - sectors are protected from program, erase, and lock status changes wp#=1 - the sector lock-down function is disabled - an individual lock-down sector can be un- locked and relocked via software command. once wp# goes low, sectors that previously locked-down returns to lock-down state regardless of any changes when wp# was high. 4.9.4 read sector lock status the lock status of every sector can be read through read configuration mode. to enter this mode, first com- mand write 90h to the device. the subsequent reads at sector address +00002 will output the lock status of this sector. the lock status can be read from the lowest two output pins dq0 and dq1. dq0, dq0 indicates the sec- tor lock/unlock status and set by the lock command and cleared by the unlock command. when entering lock- down, the lock status is automatically set. dq1 indi- cates lock-down status and is set by the lock-down com- mand. it cannot be further cleared by software, only by device reset or power-down. sector lock configuration table lock status data sector is unlocked dq0=0 sector is locked dq0=1 sector is locked-down dq1=1 in addition, sector lock-down is cleared only when the device is reset or powered down. 16 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 4.9.5 sector locking while erase suspend the sector lock status can be performed during an erase suspend by using standard locking command sequences to unlock, lock, or lock-down a sector. in order to change sector locking during an erase opera- tion, the write erase suspend command (b0h) is placed first; then check the status register until it is shown that the actual erase operation has been suspended. subse- quent writing the desired lock command sequence to a sector and the lock status will be changed. when com- pleting any desired lock, read or program operation, re- sume the erase operation with the erase resume com- mand (d0h). if a sector is locked or locked-down during the same 4.9.6 status register error checking the operation of locking system for this device can be used the term "state (x,y,z)" to specify locking status, where x=value of wp#, y=bit dq1 of the sector lock status register, and z=bit dq0 of the sector lock status register. dq0 indicates if a sector is locked (1) or un- locked (0). dq1 indicates if a sector has been locked- down(1) or not (0). current state erase/prog. lock command input result (next state) (x, y, z)= operation if (x, y, z)= wp# dq1 dq0 name enable ? lock unlock lock-down 0 0 0 unlocked yes (001) unchanged (011) 0 0 1 locked (default) no unchanged (000) (011) 0 1 1 locked-down no unchanged unchanged unchanged 1 0 0 unlocked yes (101) unchanged (111) 1 0 1 locked no unchanged (100) (111) 1 1 0 lock-down disabled yes (111) unchanged (111) 1 1 1 lock-down disabled no unchanged (110) unchanged table 5. sector locking state transitions sector is being placed in erase suspend, the locking sta- tus bits will be changed immediately, but when the erase is resumed, the erase operation will complete. locking operation cannot be performed during a program suspend. note: at power-up or device reset, all sectors default to locked state (001) (if wp#=0). holding wp#=0 is the recommended default. 17 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 table 6. status register definition sr.7 = write state machine status (wsms) 1 = ready 0 = busy sr.6 = sector erase suspend status (sess) 1 = sector erase suspended 0 = sector erase in progress/completed sr.5 = erase status (es) 1 = error in programming 0 = successful sector erase or clear sector lock- bits sr.4 = program status (ps) 1 = error in programming 0 = successful programming sr.3 = vpp status (vpps) 1 = vpp low detect, operation abort 0 = vpp ok sr.2 = program suspend status (pss) 1 = program suspended 0 = program in progress/completed sr.1 = sector lock status (sls) 1 =program/erase attempted an a locked sector; operation aborted 0 = no operation to locked sectors sr.0 = reserved for future enhancements (r) notes: check wsm bit first to determine word program or sec- tor erase completion, before checking program or erase status bits. when sector erase suspend is issued, wsm halts ex- ecution and sets both wsms and sess bits to "1". sess bit remains set to "1" until an sector erase resume command is issued. when this bit (sr.5) is set to "1", it means wsm is unable to verify successful sector erasure. when this bit is set to "1", wsm has attempted but failed to program a word. the wsm interrogates vpp level only after the program or erase command sequences have been entered and informs the system if vpp has not been switched on. sr.3 bit is not guaranteed to report accurate feedback between vpplk and vpp1 min. when program suspend is issued, wsm halts the ex- ecution and sets both wsms and pss bits to "1". sr.2 remains set to "1" until a program resume command is issued. if a program or erase operation is attempted to one of the locked sectors, this bit is set by the wsm. the op- eration specified is aborted and the device is returned to read status mode. sr. 0 is reserved for future use and should be masked out when polling the status register. wsms sess es ps vpps pss sls r 76543 2 1 0 18 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 5. 128-bit protection register the 128 bits of protection register are divided into two 64-bit segments. one of the segments is programmed at mxic side with unique 64-bit number; where changes are forbidden. the other segment is left empty for cus- tomer to program. once the customer segment is pro- grammed, it can be locked to prevent further reprogram- ming. 5.1 protection register read & programming the protection register is read in the configuration read mode, which follows the stated command bus defini- tions. the device is switched to this read mode by writing the read configuration command (90h). once in this mode, read cycles from addresses shown in table 7 will re- trieve the specified information. to return to read array mode, write the read array command (ffh). two-cycle protection program command is used to pro- gram protection register bits. the 64-bit number is pro- grammed 16 bits at a time. first, write c0h protection program setup command. the next write to the device will latch in address and data and program the specified location. the allowable address are also shown in table 7. refer to figure 11 for the protection register pro- gramming flowchart. any attempt to address protection program command onto undefined protection register address space will result in a status register error (sr.4 set to "1"). in addition, attempting to program to a previously locked protection register segment will result in a status regis- ter error (sr.4=1, sr.1=1). word user a7 a6 a5 a4 a3 a2 a1 a0 lock both 1 0 0 0 0 0 0 0 0 factory 1 0 0 0 0 0 0 1 1 factory 1 0 0 0 0 0 1 0 2 factory 1 0 0 0 0 0 1 1 3 factory 1 0 0 0 0 1 0 0 4 customer 1 0 0 0 0 1 0 1 5 customer 1 0 0 0 0 1 1 0 6 customer 1 0 0 0 0 1 1 1 7 customer 1 0 0 0 1 0 0 0 table 7. word-wide protection register addressing 5.2 protection register locking the user-programmable segment of the protection reg- ister is lockable by programming bit 1 of the pr-lock location to 0. bit 0 of this location is programmed to 0 at mxic to protect the unique device number. this bit is set using the protection program command to program "fffd" to pr-lock location. after these bits have been programmed, no further changes can be made to the value stored in the protection register. protection pro- gram command to a locked section will result in a status register error (program error bit sr.4 and lock error bit sr.1 will be set to 1). protection register lockout state is not reversible. protection register purpose bit address 88h~85h 4 words user program register 84h~81h 4 wo rds factory program register 80h(bit0 & bit1) protection register lock table 8. protection register memory map notes: 1. set address bit a19-a15=1 for top boot device. 2. set address bit a19-a15=0 for bottom boot device. 3. the address not specified in above are don't care. 19 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 6 electrical specifications 6.1 absolute maximum ratings operating temperature during read, sector erase, word write . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to +85 o c storage temperature . . . . . . . . . . . . . .-65 o c to +125 o c voltage on any pin (except vcc and vpp) with respect to gnd . . . . . . . . .-0.5 v to +3.7v (1) vpp supply voltage (for sector erase and word write) with respect to gnd . . . . . . . . . .-0.5v to +13.5v (1,2,4) vcc and vccq supply voltage with respect to gnd. . . . . . . . . . . . . . . . .-0.2v to +3.6v (1) output short circuit voltage . . . . . . . . . . . . .100ma (3) warning: stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and ex- tended exposure beyond the "operation conditions" may affect device reliability. 6.2.1 capacitance (1) (ta=+25 o c, f=1mhz) symbol parameter min. max. unit notes ta operating temperature -40 +85 o c vcc1 vcc supply voltage 2.7 3.6 v 1 vccq i/o supply voltage 2.7 3.6 v 1 vpp1 supply voltage 1.65 3.6 v 1 vpp2 supply voltage 11.4 12.6 v 1,2 cycling sector erase cycling 100,000 2 6.2 operating conditions (temperature and vcc operating conditions) symbol parameter typ. max. unit t est condition cin input capacitance 6 8 pf vin=0.0v cout output capacitance 10 12 pf vout=0.0v note: 1.sampled, not 100% tested. 1. minimum dc voltage is -0.5v on input/output pins. during transitions, this level may undershoot to -2.0v for periods <20ns. maximum dc voltage on input/out- put pins to vcc+0.5v which during transition; may overshoot to vcc+2.0v for periods <20ns. 2. maximum dc voltage on vpp may overshoot to +14.0v for periods <20ns. 3. output shorted for no more than one second. no more than one output shorted at a time. 4. vpp voltage is normally 1.65v~3.6v. connection to supply of 11.4v~12.6v can only be done for 1000 cycles on the main sectors and 2500 cycles on the parameter sectors during program/erase. vpp may be connected to 12v for a total of 80 hours maximum. note: 1. vcc and vccq must share the same supply when they are in the vcc1 range. 2. applying vpp=11.4~12.6v during a program/erase can only be done for a maximum of 1000 cycles on the main sectors and 2500 cycles on the parameter sectors. vpp may be connected to 12v for a total of 80 hours maximum. 20 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 6.2.2 ac input/output test conditions figure 1. transient input/output reference waveform test points vccq/2 output note:ac test inputs are driven at vccq/2 for a logic "1" and 0.0v for a logic "0". vccq 0.0 input vccq/2 figure 2. switching test circuits test specifications test condition 70 90 110 unit output load 1 ttl gate output load capacitance, cl 30 100 100 pf (including jig capacitance) input rise and fall times 5 ns input pulse levels 0.0-3.0 v input timing measurement 1.5 v reference levels output timing measurement 1.5 v reference levels device under test diodes=in3064 or equivalent cl 6.2k ohm 2.7k ohm 3.3v 21 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 6.2.3 ac characteristic -- read only operation (1) -70 -90 sym. parameter notes min. max. min. max. unit tavav read cycle time 70 90 ns tavqv address to output delay 70 90 ns telqv ce# to output delay 2 70 90 ns tglqv oe# to output delay 2 20 30 ns tphqv reset# to output delay 150 150 ns telqx ce# to output in low z 3 0 0 ns tglqx oe# to output in low z 3 0 0 ns tehqz ce# to output in high z 3 20 20 ns tghqz oe# to output in high z 3 20 20 ns toh output hold from address, 3 0 0 ns ce#, or oe# change, whichever occurs first notes: 1. see ac waveform: read operations at figure 3. 2. oe# may be delayed up to telqv-tglqv after the falling edge of ce# without impact on telqv. 3. sampled, but not 100% tested. 4. see test configuration. 22 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 figure 3. read-only operation ac waveform tehqz tavav tghqz tglqv telqv telqx tavqv tphqv tglqx toh high z high z valid output address stable device and address selection data valid standby vih vil addresses(a) vih vil ce# (e) vih vil oe# (g) vih vil we# (w) vih vil reset# (p) voh vol data (d/q) 23 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 6.2.5 ac characteristic -- write operation notes: 1. write timing characteristics during erase suspend are the same as during write-only operations. 2. refer to table 5 for valid ain or din. 3. sampled, not 100% tested. 4. write pulse width (twp) is defined from ce# or we# going low (whichever goes low last) to ce# or we# going high (whichever goes high first). hence, twp=twlwh=teleh=twleh=telwh. similarly, write pulse width high (twph) is defined from ce# or we# going high (whichever goes high first) to ce# or we# going low (whichever goes low first). hence, twph=twhwl=tehel=twhel=tehwl. 5. see test configuration. -70 -90 sym. parameter note min. min. unit tphwl/tphel reset# high recovery to we#(ce#) going low 150 150 ns telwl/twlel ce#(we#) setup to we#(ce#) going low 0 0 ns twlwh/teleh we#(ce#) pulse width 4 45 60 ns tdvwh/tdveh data setup to we#(ce#) going high 2 40 50 ns tavwh/taveh address setup to we#(ce#) going high 2 50 60 ns twheh/tehwh ce#(we#) hold time from we#(ce#) high 0 0 ns twhdx/tehdx data hold time from we#(ce#) high 2 0 0 ns twhax/tehax address hold time from we#(ce#) high 2 0 0 ns twhwl/tehel we#(ce#) pulse width high 4 25 30 ns tvpwh/tvpeh vpp setup to we#(ce#) going high 3 200 200 ns tqvvl vpp hold from valid srd 3 0 0 ns tbhwh/tbheh wp# setup to we#(ce#)going high 3 0 0 ns tqvbl wp# hold from valid srd 3 0 0 ns twhgl we# high to oe# going low 3 30 30 ns 24 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 figure 4. write and erase operation ac waveform notes: 1. ce# must be toggled low when reading status register data. we# must be inactive (high) when reading status register data. a.vcc power-up and standby. b.write program or erase setup command. c.write valid address and data (for program) or erase confirm command. d.automated program or erase delay. e.read status register data (srd): reflects completed program/erase operation. f.write read array command. tvpwh (tvpeh) tqvvl twhwl (tehel) twhgl tphwl (tphel) (note 1) (note 1) teleh (twlwh) twhdx (tehdx) twheh (tehwh) telwl (twlel) tavwh (taveh) twhax (tehax) tdvwh (teveh) tbhwh (tbheh) tqvbl high z din address (a) ab cd e f vih vil oe#(g) vih vil vih vil ce#(we#)[e(w)] vih disable enable vil we#,(ce#)[w(e)] vih vil data[d/q] voh vol reset#[p] vih vil vpph1 vpph2 vpplk vil wp# vpp[v] din ain ain din valid srd 25 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 6.2.5 erase and program timing (1) vpp 1.65v-3.6v 11.4v-12.6v symbol parameter note typ(1) max typ(1) max unit tbwpb 4-kw parameter sector 2,3 0.10 0.30 0.03 0.12 s word program time tbwmb 32-kw main sector 2,3 0.8 2.4 0.24 1 s word program time twhqv1/ word program time 2,3 12 200 8 185 us tehqv1 twhqv2/ 4-kw parameter sector 2,3 0.5 4 0.4 4.0 s tehqv2 erase time twhqv3/ 32-kw main sector 2,3 1 5 0.6 5 s tehqv3 erase time twhrh1/ program suspend latency 3 15 20 15 20 us tehrh1 twhrh2/ erase su spend latency 3 15 20 15 20 us tehrh2 notes: 1. typical values measured at ta=+25 c and nominal voltage. 2. excludes external system-level overhead. 3. sampled, but not 100% tested. 26 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 ac characteristic -- under reset operation sym. parameter vcc=2.7v~3.6v unit notes min. max. tplph reset# low to reset during read 100 ns 1,3 (if reset# is tied to vcc, this specification is not applicable) tplrh1 reset# low to reset during sector erase 22 us 1,4 tplrh2 reset# low to reset during program 12 us 1,4 notes: 1. see section 3.4 for a full description of these conditions. 2. if tplph is < 100ns the device may still reset but this is not guaranteed. 3. if reset# is asserted while a sector erase or word program operation is not executing, the reset will complete within 100ns. 4. sampled, but not 100% tested. figure 5. reset waveform tplph tplrh abort complete tphqv tphwl tphel tphqv tphwl tphel vih vil reset# (p) (a) reset during read mode tplph vih vil reset# (p) (b) reset during program or sector erase, tplph < tplrh tplrh abort complete deep power- down tphqv tphwl tphel tplph vih vil reset# (p) (c) reset program or sector erase, tplph > tplrh 27 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 6.2.6 dc characteristics vcc 2.7v-3.6v sym. parameter vccq 2.7v-3.6v unit t est conditions note typ. max. ili input load current 1,2 1 ua vcc=vcc max. ; vccq=vccq max. vin=vccq or gnd ilo output leakage 1,2 0.2 10 ua vcc=vcc max. ; vccq=vccq max. current vin=vccq or gnd iccs vcc standby current 1 7 15 ua vcc=vcc max. ; ce#=reset#=vccq or during program/erase suspend wp#=vccq or gnd iccd vcc power-down 1,2 7 15 ua vcc=vcc max ; vccq=vccq max current vin=vccq or gnd reset#=gnd 0.2v iccr vcc read current 1,2,3 9 18 ma vcc=vcc max ; vccq=vccq max oe#=vih, ce#=vil, f=5mhz, iout=0ma, inputs=vil or vih ippd vpp deep power- 1 0.2 5 ua reset#=gnd 0.2v down current vpp < vcc ippr vpp read current 1,4 2 15 ua vpp < vcc 50 200 ua vpp > vcc iccw+ vcc+vpp program 1,4 18 55 ma vpp=vpp1, program in progress ippw current 10 30 ma vpp=vpp2(12v), program in progress icce+ vcc+vpp erase 1,4 21 45 ma vpp=vpp1, erase in progress ippe current 16 45 ma vpp=vpp2(12v), erase in progress icces vcc program 1,4 7 15 ua ce#=vcc, or or erase suspend program or erase suspend in progress iccws current vil input low voltage -0.4 vcc*0.22v v vih input high voltage 2.0 vccq +0.3v v vol output low voltage -0.1 0.1 v vcc=vcc min, vcc=vccq min iol=100ua voh output high voltage vccq v vcc=vcc min, vcc=vccq min -0.1v ioh=-100ua vpplk vpp lock-out voltage 6 1.0 v co mplete write protection vpp1 vpp during program/ 6 1.65 3.6 v vpp2 erase operations 6 11.4 12.6 v vlko vcc prog/erase 1.5 v lock voltage vlko2 vccq prog/erase 1.2 v lock voltage 28 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 notes: 1. all currents are in rms unless otherwise noted. typical values at nominal vcc, ta=+25 c. 2. the test conditions vcc max, vccq max, vcc min, and vccq min refer to the maximum or minimum vcc or vccq voltage listed at the top of each column. 3. power savings (mode) reduces iccr to approximately standby levels in static operation (cmos inputs). 4. sampled, but not 100% tested. 5. icces and iccws are specified with device de-selected. if device is read while in erase suspend, current draw is sum of icces and iccr. if the device is read while in program suspend, current draw is the sum of iccws and iccr. 6. erase and program are inhibited when vpp 30 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 figure 7. program suspend/resume flowchart bus command comments operation write program data=b0h suspend addr=x write read status data=70h addr=x read status register data toggle ce# or oe# to update status register data addr=x standby check sr.7 1=wsm ready 0=wsm busy stanby check sr.2 1=program suspended 0=program completed write read array data=ffh addr=x read read array data from sector other than the one being programmed. write program data=d0h resume addr=x start program write resumed program completed write b0h write 70h read status register 0 0 1 write ffh read array data write d0h sr.7= 1 sr.2= ye s no done reading read array data write ffh 31 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 figure 8. automated sector erase flowchart bus command comments operation write erase setup data=20h addr=within sector to be erased write erase data=d0h confirm addr=within sector to be erased read status register data toggle ce# or oe# to update status register data standby check sr.7 1=wsm ready 0=wsm busy repeat for subsequent sector erasures. full status check can be done after each sector erase or after a sequence of sector erasures. write ffh after the last write operation to reset device to read array mode. bus command comments operation standby check sr.3 1=vpp low detect standby check sr.4, 5 both 1=command sequence error standby check sr.5 1=sector erase error standby check sr.1 1=attempted erase of locked sector- erase aborted sr.1 and sr.3 must be cleared, if set during an erase attempt, before further attempts are allowed by the write state machine. sr.1,3,4,5 are only cleared by the clear status reg- ister command, in cases where multiple bytes are erased before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. start write 20h write d0h and sector address full status check if desired sector erase complete read status register suspend erase loop 0 no ye s 1 sr.7= suspend erase read status register data(see above) full status check procedure sector erase successful sr.3= 0 0 0 0 vpp range error 1 command sequence error 1 sector erase error 1 sr.4,5= sr.5= attempted erase of locked sector - aborted 1 sr.1= 32 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 figure 9. erase suspend/resume flowchart bus command comments operation write erase data=b0h suspend addr=x write read status data=70h addr=x read status register data toggle ce# or oe# to update status register data addr=x standby check sr.7 1=wsm ready 0=wsm busy stanby check sr.6 1=erase suspended 0=erase completed write read array data=ffh addr=x read read array data from sector other than the one being erased. write erase data=d0h resume addr=x start erase write resumed erase completed write b0h write 70h read status register 0 0 1 write ffh read array data write d0h sr.7= 1 sr.6= ye s no done reading read array data write ffh 33 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 figure 10. locking operations flowchart bus command comments operation write config. setup data=60h addr=x write lock, unlock data=01h (sector lock) or lockdown d0h(sector unlock) 2fh(sector lockdown) addr=within sector to lock write read status data=70h (optional) register addr=x read status register register (optional) addr=x stanby check status register (optional) 80h=no error 30h=lock command sequence error write read data=90h (optional) configuration addr=x read sector lock sector lock status data (optional) status addr=second addr of sector stanby confirm locking change on dq1, dq0 (see sector locking state table for valid combinations.) start locking change complete lock command sequence error write 60h (configuration setup) write 01h, d0h, or 2fh write 70h (read status register) read status register 1,1 0,0 write 90h (read configuration) read sector lock status sr.4, sr.5= ye s no locking change confirmed ? 34 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 figure 11. protection register programming flowchart start write c0h (protection reg. program setup) full status check if desired read status register write protect. register address/data no ye s sr.7=1 ? program ccomplete read status register data(see above) full status check procedure program successful sr.3, sr.4= vpp range error 1,1 protection register programming error 0,1 attempted program to locked register aborted 1,1 sr.1, sr.4= sr.1, sr.4= bus command comments operation write protection data=c0h program setup write protection data=data to program program addr=location to program read status register data toggle ce# or oe# to update status register data standby check sr.7 1=wsm ready 0=wsm busy protection program operations can only be addressed within the protection register address space. addresses outside the defined space will return an error. repeat for subsequent programming operations. sr full status check can be done after each program or after a sequence of program operations. write ffh after the last operation to reset device to read array mode. bus command comments operation standby sr.1, sr.3, sr.4 0 1 1 vpp low standby 0 0 1 prot. reg. prog. error stanby 1 0 1 register locked: aborted sr.3 must be cleared, if set during a program at- tempt, before further attempts are allowed by the write state machine. sr.1,3,4 are only cleared by the clear status regis- ter command, in cases of multiple protection register program operations before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. 35 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 7 vpp program and erase voltage mx28f160c3bt/b product provides in-system program- ming and erase in the 1.65v~3.6v of vpp range. in ad- dition, vpp pin on 12v provides fast production program- ming. 7.1 vpp fast manufacturing programming when vpp is between 1.65v and 3.6v, all program and erase current is drawn through the vcc pin. if vpp is driven by a logic signal, vih=1.65v. that is, vpp must remain above 1.65v to perform in-system flash update/ modifications. when vpp is connected to a 12v power supply, the device draws program and erase current di- rectly from the vpp pin. 7.2 protection under vpp 37 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 table 9-3. cfi mode: device geometry data values description address h data h device size (2 n bytes) 27 0015 flash device interface code (asynchronous x16) 28 0001 29 0000 maximum number of bytes in write buffer=2 n (not supported) 2a 0000 2b 0000 number of erase sector regions within device (one or more continuous 2c 0002 same-size erase sectors at one sector region) tb erase sector region 1 information 2d 1e 07 [2e,2d] = number of same-size sectors in region 1-1 2e 00 00 [30, 2f] = region erase sector size in multiples of 256-bytes 2f 00 20 30 01 00 tb erase sector region 2 information 31 07 1e [32,31] = number of same-size sectors in region 2-1 32 00 00 [34,33] = region erase sector size in multiples of 256-bytes 33 20 00 34 00 01 38 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 table 9-4. cfi mode: primary vendor-specific extended query data values description address h data h query-unique ascii string "pri" 35 0050 36 0052 37 0049 major version number, ascii 38 0031 minor version number, ascii 39 0030 optional feature & command support 3a 66 bit 0 chip erase supported (1=yes, 0=no) 3b 00 bit 1 suspend erase supported (1=yes, 0=no) 3c 00 bit 2 suspend program supported (1=yes, 0=no) 3d 00 bit 3 lock/unlock supported (1=yes, 0=no) bit 4 queued erase supported (1=yes, 0=no) bit 5 instant individual sector locking supported (1=yes, 0=no) bit 6 protection bits supported (1=yes, 0=no) bit 7 page mode read supported (1=yes, 0=no) bit 8 synchronous read support (1=yes, 0=no) bits 9-31 revered for future use; undefined bits are "0" supported functions after suspend 3e 01 bit 0 program supported after erase suspend (1=yes, 0=no) bit 1-7 reserved for other supported options; undefined bits are "0" sector lock status 3f 03 define which bits in the sector status register section of the query are 40 00 implemented. bit 0 sector lock status register lock/unlock bit (bit 0) active; (1=yes, 0=no) bit 1 sector lock status register lock-down bit (bit 1) active; (1=yes, 0=no) bits 2-15 reserved for future use. undefined bits are "0". vcc logic supply optimum program/erase voltage (highest performance) 41 33 bits 7-4 bcd value in volts bits 3-0 bcd value in 100mv vpp supply optimum program/erase voltage 42 c0 bits 7-4 hex value in volts bits 3-0 bcd value in 100mv 39 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 order information part no. access time operating standby package (ns) read current max.(ma) current max.(ua) mx28f160c3bttc-70 70 18 15 48 pin tsop MX28F160C3BBtc-70 70 18 15 48 pin tsop mx28f160c3bttc-90 90 18 15 48 pin tsop MX28F160C3BBtc-90 90 18 15 48 pin tsop mx28f160c3btti-70 70 18 15 48 pin tsop MX28F160C3BBti-70 70 18 15 48 pin tsop mx28f160c3btti-90 90 18 15 48 pin tsop MX28F160C3BBti-90 90 18 15 48 pin tsop mx28f160c3btxac-70 70 18 15 48 ball csp MX28F160C3BBxac-70 70 18 15 48 ball csp mx28f160c3btxac-90 90 18 15 48 ball csp MX28F160C3BBxac-90 90 18 15 48 ball csp mx28f160c3btxai-70 70 18 15 48 ball csp MX28F160C3BBxai-70 70 18 15 48 ball csp mx28f160c3btxai-90 90 18 15 48 ball csp MX28F160C3BBxai-90 90 18 15 48 ball csp mx28f160c3bttc-70g 70 18 15 48 pin tsop MX28F160C3BBtc-70g 70 18 15 48 pin tsop mx28f160c3bttc-90g 90 18 15 48 pin tsop MX28F160C3BBtc-90g 90 18 15 48 pin tsop mx28f160c3btti-70g 70 18 15 48 pin tsop MX28F160C3BBti-70g 70 18 15 48 pin tsop mx28f160c3btti-90g 90 18 15 48 pin tsop MX28F160C3BBti-90g 90 18 15 48 pin tsop mx28f160c3btxac-70g 70 18 15 48 ball csp MX28F160C3BBxac-70g 70 18 15 48 ball csp mx28f160c3btxac-90g 90 18 15 48 ball csp MX28F160C3BBxac-90g 90 18 15 48 ball csp mx28f160c3btxai-70g 70 18 15 48 ball csp MX28F160C3BBxai-70g 70 18 15 48 ball csp mx28f160c3btxai-90g 90 18 15 48 ball csp MX28F160C3BBxai-90g 90 18 15 48 ball csp 40 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 package information 41 p/n:pm1085 mx28f160c3bt/b rev. 1.0, mar. 18, 2004 mx28f160c3bt/b m acronix i nternational c o., l td . headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office: tel:+32-2-456-8020 fax:+32-2-456-8021 japan office: tel:+81-44-246-9100 fax:+81-44-246-9105 singapore office: tel:+65-348-8385 fax:+65-348-8096 taipei office: tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-453-8088 fax:+1-408-453-8488 chicago office: tel:+1-847-963-1900 fax:+1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice. |
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